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d a t a sh eet product speci?cation supersedes data of 2000 nov 22 2004 feb 23 integrated circuits pcf8812 65 102 pixels matrix lcd driver
2004 feb 23 2 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 pin functions 7.1 pin functions 7.1.1 row 0 to row 64 row driver outputs 7.1.2 col 0 to col 101 column driver outputs 7.1.3 v ss1 and v ss2 : negative power supply rails 7.1.4 v dd1 to v dd3 : positive power supply rails 7.1.5 v lcdin : lcd power supply 7.1.6 v lcdout : lcd power supply 7.1.7 v lcdsense : voltage multiplier regulation input (v lcd ) 7.1.8 test1 to test5: test pads 7.1.9 sdin: serial data line 7.1.10 sclk: serial clock line 7.1.11 d/ c: mode select 7.1.12 sce: chip enable 7.1.13 osc: oscillator 7.1.14 res: reset 8 functional description 8.1 oscillator 8.2 address counter (ac) 8.3 display data ram (ddram) 8.4 timing generator 8.5 display address counter 8.6 lcd row and column drivers 9 addressing 9.1 data structure 10 instructions 10.1 initialization 10.2 reset function 10.3 function set 10.3.1 bit pd 10.3.2 bit v 10.3.3 bit h 10.4 display control 10.4.1 bits d and e 10.5 set y address of ram 10.6 set x address of ram 10.7 set hv-generator stages 10.8 bias system 10.9 temperature control 10.10 set v op value 11 limiting values 12 handling 13 dc characteristics 14 ac characteristics 15 application information 16 bonding pad information 16.1 pcf8812u/2da/2 16.2 pcf8812/2/f1 17 tray information 17.1 tray dimensions 18 device protection diagram 19 data sheet status 20 definitions 21 disclaimers
2004 feb 23 3 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 1 features 65 row and 102 column outputs display data ram 65 102 bits on-chip: C configurable 5 (4, 3 and 2) voltage multiplier generating v lcd (external v lcd also possible) C generation of intermediate lcd bias voltages C oscillator requires no external components (external clock also possible). external reset input pin serial interface maximum 4 mbit/s cmos compatible inputs mux rate: 1 : 65 logic supply voltage range v dd1 to v ss : C 2.5 v to 5.5 v. high voltage generator supply voltage range v dd2 to v ss and v dd3 to v ss C 2.5 to 4.5 v. display supply voltage range v lcd to v ss : C 4.5 to 9.0 v. low power consumption, suitable for battery operated systems temperature compensation of v lcd temperature range: t amb = - 40 c to +85 c slim chip layout, suited for chip-on-glass (cog) applications. 2 applications telecom equipment. 3 general description the pcf8812 is a low power cmos lcd controller driver, designed to drive a graphic display of 65 rows and 102 columns. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd supply and bias voltages, resulting in a minimum of external components and low power consumption. the pcf8812 interfaces to microcontrollers via a serial bus interface. 4 ordering information type number package name description version pcf8812u/2da/2 tray chip with bumps in tray - pcf8812u/2/f1 tray chip with bumps in tray -
2004 feb 23 4 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 5 block diagram mgt636 display data ram (ddram) 65 102 bits data latches column drivers shift register reset row drivers col0 to col101 pcf8812 row0 to row64 102 t1 t2 t3 t4 t5 timing generator address counter data register display address counter oscillator osc i/o buffer sce sdin sclk v lcdout vlcdsense v lcdin v ss2 v ss1 v dd1 v dd2 v dd3 high voltage generator 4 stages bias voltage generator res 1 194 2 to 15, 18 to 36, 139 to 156, 159 to 172 37 to 138 180 181 to 193 174 to 179 224 to 229 230 to 236 200 to 213 214 to 217, 221, 222 237 218 198 223 220 219 195 199 196 197 d/c 16 17 157 158 173 n.c. 65 fig.1 block diagram.
2004 feb 23 5 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 6 pinning 7 pin functions 7.1 pin functions 7.1.1 row 0 to row 64 row driver outputs these pads output the row signals. 7.1.2 col 0 to col 101 column driver outputs these pads output the column signals. 7.1.3 v ss1 and v ss2 : negative power supply rails supply rails v ss1 and v ss2 must be connected together. 7.1.4 v dd1 to v dd3 : positive power supply rails v dd2 and v dd3 are the supply voltage for the internal voltage generator. both have the same voltage and may be connected together outside of the chip. v dd1 is used as supply for the rest of the chip. v dd1 can be connected together with v dd2 and v dd3 but in this case care must be taken to respect the supply voltage range (see chapter 13). if the internal voltage generator is not used then v dd2 and v dd3 must be connected to v dd1 or connected to power. 7.1.5 v lcdin : lcd power supply positive power supply for the liquid crystal display. an external lcd supply voltage can be supplied using the v lcdin pad. in this case v lcdout has to be left open-circuit and the internal voltage generator has to be programmed to zero. if the pcf8812 is in power-down mode, the external lcd supply voltage has to be switched off. 7.1.6 v lcdout : lcd power supply positive power supply for the liquid crystal display. if the internal voltage generator is used, the two supply rails v lcdin and v lcdout must be connected together. if an external supply is used this pin must be left open-circuit. 7.1.7 v lcdsense : voltage multiplier regulation input (v lcd ) v lcdsense is the input of the internal voltage multiplier regulation. if the internal voltage generator is used then v lcdsense must be connected to v lcdout . if a external supply voltage is used then the v lcdsense can be let open-circuit or connected to ground. symbol pad description res 1 external reset input (active low) row32 to row19 2 to 15 lcd row driver outputs row0 to row18 18 to 36 lcd row driver outputs col0 to col101 37 to 138 lcd column driver outputs row50 to row33 139 to 156 lcd row driver outputs row51 to row64 159 to 172 lcd row driver outputs v dd1 174 to 179 logic supply voltage v dd3 180 internal voltage generator supply voltage v dd2 181 to 193 internal voltage generator supply voltage osc 194 oscillator input sdin 195 serial data input d/ c 196 data or command input sce 197 chip enable input (active low) test2 198 test 2 output sclk 199 serial clock input v ss2 200 to 213 negative power supply voltage 2 v ss1 214 to 217 negative power supply voltage 1 test1 218 test 1 input test5 219 test 5 input test4 220 test 4 input v ss1 221 and 222 negative power supply voltage 1 test3 223 test 3 input and output v lcdin 224 to 229 lcd supply voltage input v lcdout 230 to 236 lcd supply internal voltage multiplier output vlcdsense 237 voltage multiplier regulation input n.c. 16, 17, 157, 158 and 173 not connected
2004 feb 23 6 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 7.1.8 test1 to test5: test pads test1, test3, test4 and test5 must be connected to v ss , test2 must be left open-circuit. not accessible to user. 7.1.9 sdin: serial data line serial data input line. 7.1.10 sclk: serial clock line input for the clock signal 0 to 4 mbit/s. 7.1.11 d/ c: mode select input to select either command/address or data input. 7.1.12 sce: chip enable the enable pin allows data to be clocked in; the signal is active low. 7.1.13 osc: oscillator when the on-chip oscillator is used this input must be connected to v dd . an external clock signal, if used, is connected to this input. if the oscillator and external clock are both inhibited by connecting the osc pin to v ss the display is not clocked and may be left in a dc state. to avoid this the chip should always be put into power-down mode before stopping the clock. 7.1.14 res: reset this signal will reset the device and must be applied to properly initialize the chip; the signal is active low. 8 functional description 8.1 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required and the osc input must be connected to v dd . an external clock signal, if used, is connected to this input. 8.2 address counter (ac) the address counter assigns addresses to the display data ram for writing. the x address x6 to x0 and the y address y3 to y0 are set separately. after a write operation the address counter is automatically incremented by 1 according to the v flag (see chapter 9). 8.3 display data ram (ddram) the pcf8812 contains a 65 102 bit static ram which stores the display data. the ram is divided into 8 banks of 102 bytes (8 8 102 bits) and one bank of 102 bits (1 102 bits). during ram access, data is transferred to the ram via the serial interface. there is a direct correspondence between the x address and the column output number. 8.4 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not affected by operations on the data buses. 8.5 display address counter the display is generated by continuously shifting rows of ram data to the dot matrix lcd via the column outputs. the display status (all dots on/off and normal/inverse video) is set by bits e and d in the command display control (see table 2). 8.6 lcd row and column drivers the pcf8812 contains 65 row and 102 column drivers, which connect the appropriate lcd bias voltages in sequence to the display in accordance with the data to be displayed. figure 2 shows typical waveforms. unused outputs should be left unconnected.
2004 feb 23 7 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 mgt637 row 0 r0 (t) row 1 r1 (t) col 0 c0 (t) col 1 c1 (t) 0 v 0 v v 3 - v ss frame n frame n + 1 01234567 8... ... 64 01234567 8... ... 64 v state1 (t) v state1 (t) v state2 (t) v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd - v ss v lcd - v 2 v 4 - v 5 v ss - v 5 v 4 - v lcd v 3 - v 2 v ss - v lcd 0 v 0 v v 3 - v ss v state2 (t) v lcd - v ss v lcd - v 2 v 4 - v 5 v 4 - v lcd v 3 - v 2 v ss - v 5 v ss - v lcd fig.2 typical lcd driver waveforms. (1) v state1 (t) = c1(t) - r0(t). (2) v state2 (t) = c1(t) - r1(t).
2004 feb 23 8 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 9 addressing top of lcd mgs395 ddram bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 lcd fig.3 ddram to display mapping.
2004 feb 23 9 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 data is downloaded in bytes into the ram matrix of the pcf8812 as indicated in figs.3, 4, 5 and 6. the display ram has a matrix of 65 102 bits. the columns are addressed by the address pointer. the address ranges are: x0 to x101 (110 0101b) and y0 to y8 (1000b). addresses outside of these ranges are not allowed. in vertical addressing mode (bit v = 1) the y address increments after each byte (see fig.6). after the last y address (y8) y8 wraps around to y0 and x increments to address the next column. in horizontal addressing mode (bit v = 0) the x address increments after each byte (see fig.5). after the last x address (x101) x wraps around to x0 and y increments to address the next row. after the very last address (x101, y8) the address pointers wrap around to address x0, y0. 9.1 data structure handbook, full pagewidth mgt638 0 8 0 101 x address y address msb lsb msb lsb fig.4 ram format addressing. handbook, full pagewidth mgs397 09 110 2 3 4 5 6 7 8 0 8 917 0 101 x address y address fig.5 sequence of writing data bytes into ram with vertical addressing (v = 1).
2004 feb 23 10 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 handbook, full pagewidth mgs396 012 102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 612 613 614 714 715 716 816 817 818 0 8 917 0 101 x address y address fig.6 sequence of writing data bytes into ram with horizontal addressing (v = 0). 10 instructions the instruction format is divided into two modes: if pad d/ c (data or command select) is set low the current byte is interpreted as a command (see table 1). the general format of the data stream is shown in fig.7. if pad d/ c is set high the data bytes that follow are stored in the display data ram. after every data byte the address counter is incremented automatically. the level of the d/ c signal is read during the last bit period of each data byte. each instruction can be sent to the pcf8812 in any order. the msb of a byte is transmitted first. one possible command stream used to set-up the lcd driver is shown in fig.8. the serial interface is initialized when pad sce is high. in this state sclk clock pulses have no effect and no power is consumed by the serial interface. a negative edge on pad sce enables the serial interface and indicates the start of a data transmission. figures 9 and 10 show the serial bus protocol for the transmission of one byte and several bytes respectively: when pad sce is high, sclk clock pulses are ignored and the serial interface is initialized sdin is sampled at the positive edge of sclk pad d/ c indicates whether the byte is a command (pad d/ c = 0) or ram data (pad d/ c = 1). the state of d/ c is read during the eighth sclk pulse period if pad sce stays low after the last bit of a command or data byte, the serial interface expects bit db7 of the next byte at the next positive edge of sclk (see fig.11). if pad sclk goes low after the last data bit (bit db0), either: C a rising clock edge is required to latch the last data bit C or the last bit is latched when pad sce goes high (see fig.12). you can set the address pointer to a specific address, using the appropriate commands, at any time (see table 1). a special case is when the current address pointer location is at the last address (x101 and y8). in this case you must send a no operation command (nop) before setting the new address. a reset pulse res interrupts the transmission. no data is written into the ram and the registers are cleared. if pad sce is low after the positive edge of pad res, the serial interface is ready to receive bit 7 of a command or data byte as shown in fig.11.
2004 feb 23 11 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 handbook, halfpage mgt639 data data msb (db7) lsb (db0) fig.7 general format of data stream. handbook, full pagewidth mgt640 temperature control set v op bias system function set (h = 1) x address y address display control function set (h = 0) fig.8 example of serial data stream. handbook, full pagewidth sce d/c sclk sdin db7 db6 db5 db4 db3 db2 db1 db0 mgt641 fig.9 serial bus protocol transmission of one byte.
2004 feb 23 12 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 handbook, full pagewidth sce d/c sclk sdin db7 db6 db5 db4 db3 db2 db1 db0 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 db5 mgt642 fig.10 serial bus protocol transmission of several bytes. mgt644 sce res d/c sclk sdin db7 db6 db5 db4 db3 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 db5 db4 fig.11 serial interface reset ( res). handbook, full pagewidth sce res d/c sclk sdin db7 db6 db5 db4 db3 db2 db1 db0 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 db5 mgt643 fig.12 serial interface enable ( sce).
2004 feb 23 13 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 table 1 instruction set note 1. see table 2 for explanation of symbols. instruction d/c command byte (1) description db7 db6 db5 db4 db3 db2 db1 db0 (h=0or1) nop 000000000no operation function set 000100pdvhpow er-down control; entry mode; extended instruction set control (h) write data 1 d7 d6 d5 d4 d3 d2 d1 d0 writes data to display ram (h=0) reserved 0000001xxdo not use display control 000001d0e sets display con?guration set v op range 00001000prsv lcd programming range select set y address of ram 00100y 3 y 2 y 1 y 0 sets y address of ram; 0 y 8 set x address of ram 0 1 x6 x5 x4 x3 x2 x1 x0 sets x address part of ram; 0 x 101 (h=1) reserved 000000001do not use reserved 00000001xdo not use temperature control 0000001tc 1 tc 0 set temperature coef?cient (tcx) set voltage multiplier factor 0000010s 1 s 0 # of hv-gen voltage multiplication bias system 000010bs 2 bs 1 bs 0 set bias system (bsx) reserved 0 0 1 xxxxxxdo not use (reserved for test) set v op 01v op 6v op 5v op 4v op 3v op 2v op 1v op 0 write v op to register
2004 feb 23 14 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 table 2 explanations for symbols in table 1 bit 0 1 reset state pd chip is active chip is in power-down mode 1 v horizontal addressing vertical addressing 0 h use basic instruction set use extended instruction set 0 prs v lcd programming range; low v lcd programming range; high 0 d, e 00 display blank d = 0 10 normal mode 01 all display segments on e = 0 11 inverse video mode tc1 to tc0 00 v lcd temperature coef?cient 0 tc1 to tc0 = 00 01 v lcd temperature coef?cient 1 10 v lcd temperature coef?cient 2 11 v lcd temperature coef?cient 3 s1 to s0 00 2 voltage multiplier s1 to s0 = 00 01 3 voltage multiplier 10 4 voltage multiplier 11 5 voltage multiplier v op 6to v op 0 v lcd programming v op 6tov op 0 = 0000000 bs2 to bs0 bias system bs2 to bs0 = 000 10.1 initialization immediately following power-on, all internal registers as well as the ram content are undefined; a reset pulse must be applied. reset is accomplished by applying an external reset pulse (active low) at the pad res. when reset occurs within the specified time, all internal registers are reset, however the ram is still undefined. the state after reset is described in section 10.2. the res input must be 0.3v dd when v dd reaches v dd(min) (or higher) within a maximum time t vhrl after v dd going high (see fig.16). 10.2 reset function after reset the lcd driver has the following state: power-down mode (bit pd = 1) horizontal addressing (bit v = 0) normal instruction set (bit h = 0) display blank (bi te=d=0) address counter bits x6 to x0 = 0; bits y3 to y0 = 0 temperature control mode (bits tc1 to tc0 = 0) bias system (bits bs2 to bs0 = 0) v lcd is equal to 0; the hv-generator is switched off (bits v op 6tov op 0 = 0 and bit prs = 0) after power-on; ram data is undefined; the reset signal does not change ram content all lcd outputs at v ss (display off).
2004 feb 23 15 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 10.3 function set 10.3.1 b it pd when bit pd = 0: all lcd outputs at v ss (display off) bias generator and v lcd generator off; v lcd can be disconnected oscillator off (external clock possible) serial bus; command; etc. function ram contents not cleared; ram data can be written v lcd discharged to v ss in power-down mode. 10.3.2 b it v when bit v = 0, the horizontal addressing is selected. the data is written into the ddram as shown in fig.5. when bit v = 1, the vertical addressing is selected. the data is written into the ddram as shown in fig.6. 10.3.3 b it h when bit h = 0 the commands display control, set y address, set x address and set the prs bit (low or high range of the high voltage generator) can be performed, when bi th=1the other commands can be executed. the commands write data and function set can be executed when bi th=0 or 1. 10.4 display control 10.4.1 b its d and e the bits d and e select the display mode (see table 2). 10.5 set y address of ram bits y[3:0] define the y address vector address of the display ram (see table 3). table 3 x or y address range (note 1) note 1. in bank 8 only the lsb is accessed. 10.6 set x address of ram the x address points to the columns. the range of x is 0 to 101 (65h). 10.7 set hv-generator stages the pcf8812 incorporates a software configurable voltage multiplier. after reset ( res) the voltage multiplier is set to 2 v dd2 . other voltage multiplier factors are set via the command set voltage multiplier factor (see tables 1 and 2). y3 y2 y1 y0 content allowed x range 0000 bank 0 (display ram) 0 to 101 0001 bank 1 (display ram) 0 to 101 0010 bank 2 (display ram) 0 to 101 0011 bank 3 (display ram) 0 to 101 0100 bank 4 (display ram) 0 to 101 0101 bank 5 (display ram) 0 to 101 0110 bank 6 (display ram) 0 to 101 0111 bank 7 (display ram) 0 to 101 1000 bank 8 (display ram) 0 to 101
2004 feb 23 16 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 10.8 bias system the bias voltage levels are set in the ratio of r -r-nr-r-r giving a bias system. different multiplex rates require different factors n (see table 4). this is programmed by bs2 to bs0. for mux1 to mux65 the optimum bias value n is given by: resulting in 1 / 9 bias. table 4 programming the required bias system table 5 lcd bias voltage bs2 bs1 bs0 n recommended mux rate 00071to100 00161to80 01051to65 01141to48 10031to40 or 1to34 10121to24 11011to18 or 1to16 11101to10or 1to9 or 1 to 8 symbol bias voltages bias voltages for n = 5 ( 1 / 9 bias) v1 v lcd v lcd v2 8 / 9 v lcd v3 7 / 9 v lcd v4 2 / 9 v lcd v5 1 / 9 v lcd v6 v ss v ss 1 n4 + () ----------------- n653 C 5.062 5 === n3 + () n4 + () ----------------- n2 + () n4 + () ----------------- 2 n4 + () ----------------- 1 n4 + () -----------------
2004 feb 23 17 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 10.9 temperature control due to the temperature dependency of the liquid crystals viscosity the lcd controlling voltage v lcd must be increased with lower temperature to maintain optimum contrast. there are 4 different temperature coefficients available in the pcf8812 (see fig.13). the coefficients are selected by bits tc1 to tc0. table 6 shows the typical values of the different temperature coefficients. the coefficients are proportional to the programmed v lcd . 10.10 set v op value the operating voltage v lcd can be set by software. the generated voltage is dependent on temperature, programmed temperature coefficient (tc) and the programmed voltage at reference temperature (t cut ). (1) the voltage at reference temperature v lcd (t = t cut ) can be calculated as follows: (2) the parameters are explained in table 6. the maximum voltage that can be generated is dependent on the v dd2 voltage and the display load current. two overlapping v lcd ranges are selectable via the command hv-gen control. for the low (prs = 0) range a = a 1 and for the high (prs = 1) range a = a 2 with steps equal to b in both ranges. it should be noted that the charge pump is turned off if v op 6 to 0 and the bit prs are all set to zero (see fig.14). for mux 1 to 65 the optimum operating voltage of the liquid can be calculated as follows; (3) where v th is the threshold voltage of the liquid crystal material used. table 6 typical values for parameters for the hv-generator programming as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd (9 v) the user has to ensure, while setting the v op register and selecting the temperature compensation (tc), that under all conditions and including all tolerances that v lcd remains below 9 v. handbook, halfpage mgs402 t v lcd t cut fig.13 temperature coefficients. v lcd t () av op b + () 1tt cut C () tc + () = v lcd tt cut = () av op b + () = symbol value unit a1 2.94 (bit prs = 0) v a2 6.75 (bit prs = 1) v b 0.03 v t cut 27 c v lcd 165 + 21 1 65 ---------- C ? ?? --------------------------------------- v th 6.85 v th ==
2004 feb 23 18 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 mgs658 00h 01h 02h a 1 + b a 2 a 1 v lcd (v) b 03h 04h 05h 06h . . . 5fh 6fh 7fh 00h 01h 02h 03h 04h 05h 06h . . . 5fh 6fh 7fh v op low ( prs = 0 ) high ( prs = 1 ) charge pump off fig.14 v op programming of pcf8812 (at t = t cut ). v op 6 to 0 (programmed) [00h to 7fh; programming range low and high].
2004 feb 23 19 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 11 limiting values in accordance with the absolute maximum rating system (iec 60134); see notes 1 and 2 notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unless otherwise specified. all voltages are referenced to v ss unless otherwise specified. 3. human body model: r s = 1.5 k w ; c = 100 pf. 4. machine model: r s =10 w ; c = 200 pf; l = 0.75 mh. 12 handling inputs and outputs are protected against electrostatic discharge in normal handling. however it is good practice to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter conditions min. max. unit v dd1 supply voltage - 0.5 +6.5 v v dd2, v dd3 supply voltage for internal voltage generator - 0.5 +4.5 v v lcd lcd supply voltage range - 0.5 +9.0 v v i all input voltages - 0.5 v dd + 0.5 v i ss ground supply current - 50 +50 ma i i , i o dc input or output current - 10 +10 ma p tot total power dissipation - 300 mw p o power dissipation per output - 30 mw t stg storage temperature - 65 +150 c v esd electrostatic handling voltage note 3 - 1900 v note 4 - 200 v
2004 feb 23 20 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 13 dc characteristics v dd = 2.5 to 5.5 v; v ss =0v; v lcd = 4.5 to 9.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v dd1 supply voltage 2.5 - 5.5 v v dd2, v dd3 supply voltage for internal voltage generator lcd voltage internally generated (voltage generator enabled) 2.5 - 4.5 v v lcdin lcd input supply voltage lcd voltage externally supplied (voltage generator disabled) 4.5 - 9.0 v v lcdout lcd output supply voltage lcd voltage internally generated (voltage generator enabled); note 1 4.5 - 9.0 v i dd(tot) total supply current normal display mode; v dd1 = 2.8 v; v lcd = 7.6 v; f sclk = 0; t amb =25 c; no display load; 4 charge pump; notes 2 and 3 - 220 350 m a power-down mode; with internal or external v lcd supply voltage; note 4 - 1.5 -m a i lcdin supply current from external v lcd v dd1 = 2.8 v; v lcd = 7.6 v; f sclk = 0; t = 25 c; no display load; notes 2, 3 and 5 - 30 -m a logic v il low-level input voltage v ss - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd v i il input leakage current v i =v dd1 or v ss1 - 1 - +1 m a column and row outputs r col column output resistance i l =10 m a; outputs tested one at a time - 12 20 k w r row row output resistance i l =10 m a; outputs tested one at a time - 12 20 k w v bias(col) column bias tolerance - 100 0 +100 mv v bias(row) row bias tolerance - 100 0 +100 mv
2004 feb 23 21 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 notes 1. the maximum possible v lcd voltage that may be generated is dependent on the supply voltage to the internal voltage generator, temperature and (display) load. 2. internal clock. 3. f sclk = 0 means no serial clock. 4. during power-down all static currents are switched off. 5. if external v lcd ; the display load current is not transmitted to i dd . 6. tolerance depends on the temperature; (typical null at t amb =27 c, maximum tolerance values are measured at the temperature range limit, maximum tolerance is proportional to v lcd ). 7. for tc1 to tc3. 14 ac characteristics v dd = 2.5 to 5.5 v; v ss =0v; v lcd = 4.5 to 9.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. lcd supply voltage generator v lcd(tol) v lcd tolerance internally generated v dd1 = 2.8 v; v lcd = 7.6 v; f sclk = 0; t amb =25 c; display load = 10 m a; notes 3, 6 and 7 - 300 0 +300 mv tc v lcd temperature coef?cient v dd1 = 2.8 v; f sclk =0; t amb = - 20 to +70 c; display load = 10 m a; note 3 coefficient 0 - 0 10 - 3 - 1/ c coefficient 1 -- 0.76 10 - 3 - 1/ c coef?cient 2 -- 1.05 10 - 3 - 1/ c coef?cient 3 -- 2.10 10 - 3 - 1/ c symbol parameter conditions min. typ. max. unit f osc oscillator frequency v dd1 = 2.8 v; t amb = - 20 to +70 c 223867 khz f clk(ext) external clock frequency 20 38 67 khz f frame frame frequency f osc or f clk(ext) = 38 khz; note 1 - 73 - hz t vhrl v dd to res low see fig.16 0 - 1 m s t rw res low pulse width see fig.16 500 -- ns serial bus timing characteristics; see fig.15 f sclk clock frequency v dd1 = 3.0 v 10 %; all signal timing is based on 20 % to 80 % of v dd and a maximum rise and fall time of 10 ns 0 - 4.0 mhz t cyc(clk) clock cycle time 250 -- ns t pwh1 sclk pulse width high 100 -- ns t pwl1 sclk pulse width low 100 -- ns t s2 sce set-up time 60 -- ns t h2 sce hold time 100 -- ns t pwh2 sce minimum high time 100 -- ns symbol parameter conditions min. typ. max. unit
2004 feb 23 22 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 notes 1. 2. t h5 is the time from the previous sclk positive edge (irrespective of the state of sce) to the negative edge of sce (see fig.15). t h5 sce start hold time note 2 100 -- ns t s3 d/ c set-up time 100 -- ns t h3 d/ c hold time 100 -- ns t s4 sdin set-up time 100 -- ns t h4 sdin hold time 100 -- ns symbol parameter conditions min. typ. max. unit f frame f clk(ext) 520 --------------- - = mgt645 t h4 t pwh1 t pwl1 t h3 t s4 t s2 t s3 t s2 t h2 t h5 t cyc(clk) (t h5 ) t pwh2 sce d/c sclk sdin fig.15 serial interface timing.
2004 feb 23 23 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 handbook, full pagewidth mgt646 t vhrl t rw t rw t rw t rw res v dd res v dd fig.16 reset timing. 15 application information table 7 programming example step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 1 start sce is going low 2 0 0 0 1 0 0 0 0 1 function set; bit pd = 0, bit v = 0; select extended instruction set (bit h = 1 mode) 3 0 0 0 0 1 0 0 0 1 set charge pump range high (bit prs = 1) 4 010011100 setv op ;v op is set to 7.6 v 5 0 0 0 1 0 0 0 0 0 function set; bit pd = 0; bit v = 0; select normal instruction set (bit h = 0 mode) 6 0 0 0 0 0 1 1 0 0 display control; set normal mode (bit d = 1; bit e = 0). 7 1 1 1 1 1 1 0 0 0 data write; y and x are initialized to 0 by default, they are not set here mgs405
2004 feb 23 24 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 8 1 1 0 1 0 0 0 0 0 data write 9 1 1 1 1 0 0 0 0 0 data write 10 1 0 0 0 0 0 0 0 0 data write 11 1 1 1 1 1 1 0 0 0 data write 12 1 0 0 1 0 0 0 0 0 data write 13 1 1 1 1 1 1 0 0 0 data write step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 mgs406 mgs407 mgs407 mgs409 mgs410 mgs411
2004 feb 23 25 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 14 0 0 0 0 0 1 1 0 1 display control; set inverse video mode (bi td=1; bit e = 1) 15 0 1 0 0 0 0 0 0 0 set x-address of ram; set address to 0000000 16 1 0 0 0 0 0 0 0 0 data write step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 mgs412 mgs412 mgs414 handbook, full pagewidth mgt647 4 (1) display 102 65 v dd1 v dd2 v dd3 i/o c vlcd v ss2 v ss1 v lcdsense v lcdout v lcdin reset res pcf8812 102 32 33 v dd v ss c vdd fig.17 application diagram; internal charge pump is used and a single v dd . (1) 5 lines if external oscillator is used.
2004 feb 23 26 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 handbook, full pagewidth mgt648 4 (1) display 102 65 v dd1 v dd2 v dd3 v dd1 v dd2 i/o v ss c vlcd c vdd1 v ss2 v ss1 v lcdsense v lcdout v lcdin c vdd2 reset res pcf8812 102 32 33 fig.18 application diagram; internal charge pump is used and two separate v dd (v dd1 and v dd2 ). (1) 5 lines if external oscillator is used. handbook, full pagewidth mgt649 4 (1) display 102 65 v dd1 v dd2 v dd3 v dd i/o v ss v lcdin c vdd v ss2 v ss1 v lcdsense v lcdout v lcdin reset res pcf8812 102 32 33 fig.19 application diagram; external high voltage generation is used. (1) 5 lines if external oscillator is used.
2004 feb 23 27 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 the required minimum value for the external capacitors in an application with the pcf8812 are as follows: c vlcd = 100 nf (minimum) c vdd ; c vdd1 ; c vdd2 =1 m f (minimum). higher capacitor values are recommended for ripple reduction. 16 bonding pad information the pcf8812 is manufactured using n-well cmos technology. the substrate is at v ss potential. the pinning of the pcf8812 is optimized for single plane wiring, such as chip-on-glass display modules; display size: 65 102 pixels. 16.1 pcf8812u/2da/2 table 8 bonding pad dimensions name dimension pad pitch 63 m m pad size; aluminium 56 90 m m bump dimensions 42 81 15 ( 3) m m wafer thickness; without bumps 381 ( 25) m m table 9 bonding pad locations for pcf8812u/2da/2 all x and y coordinates represent the position of the centre of each pad (in m m) with respect to the origin (x/y = 0/0) of the chip (see fig.20). symbol pad coordinates xy res_b 1 +3483 +841.1 row 32 2 +3843 +841.1 row 31 3 +3906 +841.1 row 30 4 +3969 +841.1 row 29 5 +4032 +841.1 row 28 6 +4095 +841.1 row 27 7 +4158 +841.1 row 26 8 +4221 +841.1 row 25 9 +4284 +841.1 row 24 10 +4347 +841.1 row 23 11 +4410 +841.1 row 22 12 +4473 +841.1 row 21 13 +4536 +841.1 row 20 14 +4599 +841.1 row 19 15 +4662 +841.1 n.c. 16 +4788 +841.1 n.c. 17 +4819.5 - 841.1 row 0 18 +4504.5 - 841.1 row 1 19 +4441.5 - 841.1 row 2 20 +4378.5 - 841.1 row 3 21 +4315.5 - 841.1 row 4 22 +4252.5 - 841.1 row 5 23 +4189.5 - 841.1 row 6 24 +4126.5 - 841.1 row 7 25 +4063.5 - 841.1 row 8 26 +4000.5 - 841.1 row 9 27 +3937.5 - 841.1 row 10 28 +3874.5 - 841.1 row 11 29 +3811.5 - 841.1 row 12 30 +3748.5 - 841.1 row 13 31 +3685.5 - 841.1 row 14 32 +3622.5 - 841.1 row 15 33 +3559.5 - 841.1 row 16 34 +3496.5 - 841.1 row 17 35 +3433.5 - 841.1 row 18 36 +3370.5 - 841.1 col 0 37 +3244.5 - 841.1 symbol pad coordinates xy
2004 feb 23 28 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 col 1 38 +3181.5 - 841.1 col 2 39 +3118.5 - 841.1 col 3 40 +3055.5 - 841.1 col 4 41 +2992.5 - 841.1 col 5 42 +2929.5 - 841.1 col 6 43 +2866.5 - 841.1 col 7 44 +2803.5 - 841.1 col 8 45 +2740.5 - 841.1 col 9 46 +2677.5 - 841.1 col 10 47 +2614.5 - 841.1 col 11 48 +2551.5 - 841.1 col 12 49 +2488.5 - 841.1 col 13 50 +2425.5 - 841.1 col 14 51 +2362.5 - 841.1 col 15 52 +2299.5 - 841.1 col 16 53 +2236.5 - 841.1 col 17 54 +2173.5 - 841.1 col 18 55 +2110.5 - 841.1 col 19 56 +2047.5 - 841.1 col 20 57 +1984.5 - 841.1 col 21 58 +1921.5 - 841.1 col 22 59 +1858.5 - 841.1 col 23 60 +1795.5 - 841.1 col 24 61 +1732.5 - 841.1 col 25 62 +1606.5 - 841.1 col 26 63 +1543.5 - 841.1 col 27 64 +1480.5 - 841.1 col 28 65 +1417.5 - 841.1 col 29 66 +1354.5 - 841.1 col 30 67 +1291.5 - 841.1 col 31 68 +1228.5 - 841.1 col 32 69 +1165.5 - 841.1 col 33 70 +1102.5 - 841.1 col 34 71 +1039.5 - 841.1 col 35 72 +976.5 - 841.1 col 36 73 +913.5 - 841.1 col 37 74 +850.5 - 841.1 col 38 75 +787.5 - 841.1 col 39 76 +724.5 - 841.1 symbol pad coordinates xy col 40 77 +661.5 - 841.1 col 41 78 +598.5 - 841.1 col 42 79 +535.5 - 841.1 col 43 80 +472.5 - 841.1 col 44 81 +409.5 - 841.1 col 45 82 +346.5 - 841.1 col 46 83 +283.5 - 841.1 col 47 84 +220.5 - 841.1 col 48 85 +157.5 - 841.1 col 49 86 +94.5 - 841.1 col 50 87 - 31.5 - 841.1 col 51 88 - 94.5 - 841.1 col 52 89 - 157.5 - 841.1 col 53 90 - 220.5 - 841.1 col 54 91 - 283.5 - 841.1 col 55 92 - 346.5 - 841.1 col 56 93 - 409.5 - 841.1 col 57 94 - 472.5 - 841.1 col 58 95 - 535.5 - 841.1 col 59 96 - 598.5 - 841.1 col 60 97 - 661.5 - 841.1 col 61 98 - 724.5 - 841.1 col 62 99 - 787.5 - 841.1 col 63 100 - 850.5 - 841.1 col 64 101 - 913.5 - 841.1 col 65 102 - 976.5 - 841.1 col 66 103 - 1039.5 - 841.1 col 67 104 - 1102.5 - 841.1 col 68 105 - 1165.5 - 841.1 col 69 106 - 1228.5 - 841.1 col 70 107 - 1291.5 - 841.1 col 71 108 - 1354.5 - 841.1 col 72 109 - 1417.5 - 841.1 col 73 110 - 1480.5 - 841.1 col 74 111 - 1543.5 - 841.1 col 75 112 - 1606.5 - 841.1 col 76 113 - 1732.5 - 841.1 col 77 114 - 1795.5 - 841.1 col 78 115 - 1858.5 - 841.1 symbol pad coordinates xy
2004 feb 23 29 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 col 79 116 - 1921.5 - 841.1 col 80 117 - 1984.5 - 841.1 col 81 118 - 2047.5 - 841.1 col 82 119 - 2110.5 - 841.1 col 83 120 - 2173.5 - 841.1 col 84 121 - 2236.5 - 841.1 col 85 122 - 2299.5 - 841.1 col 86 123 - 2362.5 - 841.1 col 87 124 - 2425.5 - 841.1 col 88 125 - 2488.5 - 841.1 col 89 126 - 2551.5 - 841.1 col 90 127 - 2614.5 - 841.1 col 91 128 - 2677.5 - 841.1 col 92 129 - 2740.5 - 841.1 col 93 130 - 2803.5 - 841.1 col 94 131 - 2866.5 - 841.1 col 95 132 - 2929.5 - 841.1 col 96 133 - 2992.5 - 841.1 col 97 134 - 3055.5 - 841.1 col 98 135 - 3118.5 - 841.1 col 99 136 - 3181.5 - 841.1 col 100 137 - 3244.5 - 841.1 col 101 138 - 3307.5 - 841.1 row 50 139 - 3433.5 - 841.1 row 49 140 - 3496.5 - 841.1 row 48 141 - 3559.5 - 841.1 row 47 142 - 3622.5 - 841.1 row 46 143 - 3685.5 - 841.1 row 45 144 - 3748.5 - 841.1 row 44 145 - 3811.5 - 841.1 row 43 146 - 3874.5 - 841.1 row 42 147 - 3937.5 - 841.1 row 41 148 - 4000.5 - 841.1 row 40 149 - 4063.5 - 841.1 row 39 150 - 4126.5 - 841.1 row 38 151 - 4189.5 - 841.1 row 37 152 - 4252.5 - 841.1 row 36 153 - 4315.5 - 841.1 row 35 154 - 4378.5 - 841.1 symbol pad coordinates xy row 34 155 - 4441.5 - 841.1 row 33 156 - 4504.5 - 841.1 n.c. 157 - 4819.5 - 841.1 n.c. 158 - 4788 - 841.1 row 51 159 - 4662 - 841.1 row 52 160 - 4599 - 841.1 row 53 161 - 4536 - 841.1 row 54 162 - 4473 - 841.1 row 55 163 - 4410 - 841.1 row 56 164 - 4347 - 841.1 row 57 165 - 4284 - 841.1 row 58 166 - 4221 - 841.1 row 59 167 - 4158 - 841.1 row 60 168 - 4095 - 841.1 row 61 169 - 4032 - 841.1 row 62 170 - 3969 - 841.1 row 63 171 - 3906 - 841.1 row 64 172 - 3843 - 841.1 n.c. 173 - 3645 - 841.1 v dd1 174 - 3501 - 841.1 v dd1 175 - 3429 - 841.1 v dd1 176 - 3357 - 841.1 v dd1 177 - 3285 - 841.1 v dd1 178 - 3213 - 841.1 v dd1 179 - 3141 - 841.1 v dd3 180 - 2925 - 841.1 v dd2 181 - 2781 - 841.1 v dd2 182 - 2709 - 841.1 v dd2 183 - 2637 - 841.1 v dd2 184 - 2565 - 841.1 v dd2 185 - 2493 - 841.1 v dd2 186 - 2421 - 841.1 v dd2 187 - 2349 - 841.1 v dd2 188 - 2277 - 841.1 v dd2 189 - 2205 - 841.1 v dd2 190 - 2133 - 841.1 v dd2 191 - 2061 - 841.1 v dd2 192 - 1989 - 841.1 v dd2 193 - 1917 - 841.1 symbol pad coordinates xy
2004 feb 23 30 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 osc 194 - 1701 - 841.1 sdin 195 - 1485 - 841.1 d/ c 196 - 1269 - 841.1 sce 197 - 1053 - 841.1 test2 198 - 837 - 841.1 sclk 199 - 621 - 841.1 v ss2 200 - 477 - 841.1 v ss2 201 - 405 - 841.1 v ss2 202 - 333 - 841.1 v ss2 203 - 261 - 841.1 v ss2 204 - 189 - 841.1 v ss2 205 - 117 - 841.1 v ss2 206 - 45 - 841.1 v ss2 207 +27 - 841.1 v ss2 208 +99 - 841.1 v ss2 209 +171 - 841.1 v ss2 210 +243 - 841.1 v ss2 211 +315 - 841.1 v ss2 212 +387 - 841.1 v ss2 213 +459 - 841.1 v ss1 214 +603 - 841.1 v ss1 215 +675 - 841.1 v ss1 216 +747 - 841.1 v ss1 217 +819 - 841.1 test1 218 +1035 - 841.1 test5 219 +1467 - 841.1 symbol pad coordinates xy test4 220 +1827 - 841.1 v ss1 221 +1899 - 841.1 v ss1 222 +1971 - 841.1 test3 223 +2043 - 841.1 v lcdin 224 +2259 - 841.1 v lcdin 225 +2331 - 841.1 v lcdin 226 +2403 - 841.1 v lcdin 227 +2475 - 841.1 v lcdin 228 +2547 - 841.1 v lcdin 229 +2619 - 841.1 v lcdout 230 +2763 - 841.1 v lcdout 231 +2835 - 841.1 v lcdout 232 +2907 - 841.1 v lcdout 233 +2979 - 841.1 v lcdout 234 +3051 - 841.1 v lcdout 235 +3123 - 841.1 v lcdout 236 +3195 - 841.1 vlcdsense 237 +3267 - 841.1 alignment marks alignment mark 1 +4666.5 - 819.7 alignment mark 2 - 4666.5 - 819.7 alignment mark 3 - 3744 +818.7 alignment mark 4 +3744 +818.7 symbol pad coordinates xy 16.2 pcf8812/2/f1 table 10 bonding pad dimensions name dimension pad pitch 70 m m pad size; aluminium 62 100 m m bump dimensions 50 90 17.5 ( 5) m m wafer thickness; without bumps 381 ( 25) m m
2004 feb 23 31 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 table 11 bonding pad locations for pcf8812/2/f1 all x and y coordinates represent the position of the centre of each pad (in m m) with respect to the origin (x/y = 0/0) of the chip (see fig.20). symbol pad coordinates xy res 1 +3870 +934.6 row 32 2 +4270 +934.6 row 31 3 +4340 +934.6 row 30 4 +4410 +934.6 row 29 5 +4480 +934.6 row 28 6 +4550 +934.6 row 27 7 +4620 +934.6 row 26 8 +4690 +934.6 row 25 9 +4760 +934.6 row 24 10 +4830 +934.6 row 23 11 +4900 +934.6 row 22 12 +4970 +934.6 row 21 13 +5040 +934.6 row 20 14 +5110 +934.6 row 19 15 +5180 +934.6 n.c. 16 +5320 +934.6 n.c. 17 +5355 - 934.6 row 0 18 +5005 - 934.6 row 1 19 +4935 - 934.6 row 2 20 +4865 - 934.6 row 3 21 +4795 - 934.6 row 4 22 +4725 - 934.6 row 5 23 +4655 - 934.6 row 6 24 +4585 - 934.6 row 7 25 +4515 - 934.6 row 8 26 +4445 - 934.6 row 9 27 +4375 - 934.6 row 10 28 +4305 - 934.6 row 11 29 +4235 - 934.6 row 12 30 +4165 - 934.6 row 13 31 +4095 - 934.6 row 14 32 +4025 - 934.6 row 15 33 +3955 - 934.6 row 16 34 +3885 - 934.6 row 17 35 +3815 - 934.6 row 18 36 +3745 - 934.6 col 0 37 +3605 - 934.6 col 1 38 +3535 - 934.6 col 2 39 +3465 - 934.6 col 3 40 +3395 - 934.6 col 4 41 +3325 - 934.6 col 5 42 +3255 - 934.6 col 6 43 +3185 - 934.6 col 7 44 +3115 - 934.6 col 8 45 +3045 - 934.6 col 9 46 +2975 - 934.6 col 10 47 +2905 - 934.6 col 11 48 +2835 - 934.6 col 12 49 +2765 - 934.6 col 13 50 +2695 - 934.6 col 14 51 +2625 - 934.6 col 15 52 +2555 - 934.6 col 16 53 +2485 - 934.6 col 17 54 +2415 - 934.6 col 18 55 +2345 - 934.6 col 19 56 +2275 - 934.6 col 20 57 +2205 - 934.6 col 21 58 +2135 - 934.6 col 22 59 +2065 - 934.6 col 23 60 +1995 - 934.6 col 24 61 +1925 - 934.6 col 25 62 +1785 - 934.6 col 26 63 +1715 - 934.6 col 27 64 +1645 - 934.6 col 28 65 +1575 - 934.6 col 29 66 +1505 - 934.6 col 30 67 +1435 - 934.6 col 31 68 +1365 - 934.6 col 32 69 +1295 - 934.6 col 33 70 +1225 - 934.6 col 34 71 +1155 - 934.6 col 35 72 +1085 - 934.6 col 36 73 +1015 - 934.6 col 37 74 +945 - 934.6 col 38 75 +875 - 934.6 symbol pad coordinates xy
2004 feb 23 32 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 col 39 76 +805 - 934.6 col 40 77 +735 - 934.6 col 41 78 +665 - 934.6 col 42 79 +595 - 934.6 col 43 80 +525 - 934.6 col 44 81 +455 - 934.6 col 45 82 +385 - 934.6 col 46 83 +315 - 934.6 col 47 84 +245 - 934.6 col 48 85 +175 - 934.6 col 49 86 +105 - 934.6 col 50 87 - 35 - 934.6 col 51 88 - 105 - 934.6 col 52 89 - 175 - 934.6 col 53 90 - 245 - 934.6 col 54 91 - 315 - 934.6 col 55 92 - 385 - 934.6 col 56 93 - 455 - 934.6 col 57 94 - 525 - 934.6 col 58 95 - 595 - 934.6 col 59 96 - 665 - 934.6 col 60 97 - 735 - 934.6 col 61 98 - 805 - 934.6 col 62 99 - 875 - 934.6 col 63 100 - 945 - 934.6 col 64 101 - 1015 - 934.6 col 65 102 - 1085 - 934.6 col 66 103 - 1155 - 934.6 col 67 104 - 1225 - 934.6 col 68 105 - 1295 - 934.6 col 69 106 - 1365 - 934.6 col 70 107 - 1435 - 934.6 col 71 108 - 1505 - 934.6 col 72 109 - 1575 - 934.6 col 73 110 - 1645 - 934.6 col 74 111 - 1715 - 934.6 col 75 112 - 1785 - 934.6 col 76 113 - 1925 - 934.6 col 77 114 - 1995 - 934.6 symbol pad coordinates xy col 78 115 - 2065 - 934.6 col 79 116 - 2135 - 934.6 col 80 117 - 2205 - 934.6 col 81 118 - 2275 - 934.6 col 82 119 - 2345 - 934.6 col 83 120 - 2415 - 934.6 col 84 121 - 2485 - 934.6 col 85 122 - 2555 - 934.6 col 86 123 - 2625 - 934.6 col 87 124 - 2695 - 934.6 col 88 125 - 2765 - 934.6 col 89 126 - 2835 - 934.6 col 90 127 - 2905 - 934.6 col 91 128 - 2975 - 934.6 col 92 129 - 3045 - 934.6 col 93 130 - 3115 - 934.6 col 94 131 - 3185 - 934.6 col 95 132 - 3255 - 934.6 col 96 133 - 3325 - 934.6 col 97 134 - 3395 - 934.6 col 98 135 - 3465 - 934.6 col 99 136 - 3535 - 934.6 col 100 137 - 3605 - 934.6 col 101 138 - 3675 - 934.6 row 50 139 - 3815 - 934.6 row 49 140 - 3885 - 934.6 row 48 141 - 3955 - 934.6 row 47 142 - 4025 - 934.6 row 46 143 - 4095 - 934.6 row 45 144 - 4165 - 934.6 row 44 145 - 4235 - 934.6 row 43 146 - 4305 - 934.6 row 42 147 - 4375 - 934.6 row 41 148 - 4445 - 934.6 row 40 149 - 4515 - 934.6 row 39 150 - 4585 - 934.6 row 38 151 - 4655 - 934.6 row 37 152 - 4725 - 934.6 row 36 153 - 4795 - 934.6 symbol pad coordinates xy
2004 feb 23 33 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 row 35 154 - 4865 - 934.6 row 34 155 - 4935 - 934.6 row 33 156 - 5005 - 934.6 n.c. 157 - 5355 - 934.6 n.c. 158 - 5320 +934.6 row 51 159 - 5180 +934.6 row 52 160 - 5110 +934.6 row 53 161 - 5040 +934.6 row 54 162 - 4970 +934.6 row 55 163 - 4900 +934.6 row 56 164 - 4830 +934.6 row 57 165 - 4760 +934.6 row 58 166 - 4690 +934.6 row 59 167 - 4620 +934.6 row 60 168 - 4550 +934.6 row 61 169 - 4480 +934.6 row 62 170 - 4410 +934.6 row 63 171 - 4340 +934.6 row 64 172 - 4270 +934.6 n.c. 173 - 4050 +934.6 v dd1 174 - 3890 +934.6 v dd1 175 - 3810 +934.6 v dd1 176 - 3730 +934.6 v dd1 177 - 3650 +934.6 v dd1 178 - 3570 +934.6 v dd1 179 - 3490 +934.6 v dd3 180 - 3250 +934.6 v dd2 181 - 3090 +934.6 v dd2 182 - 3010 +934.6 v dd2 183 - 2930 +934.6 v dd2 184 - 2850 +934.6 v dd2 185 - 2770 +934.6 v dd2 186 - 2690 +934.6 v dd2 187 - 2610 +934.6 v dd2 188 - 2530 +934.6 v dd2 189 - 2450 +934.6 v dd2 190 - 2370 +934.6 v dd2 191 - 2290 +934.6 v dd2 192 - 2210 +934.6 symbol pad coordinates xy v dd2 193 - 2130 +934.6 osc 194 - 1890 +934.6 sdin 195 - 1650 +934.6 d/ c 196 - 1410 +934.6 sce 197 - 1170 +934.6 test2 198 - 930 +934.6 sclk 199 - 690 +934.6 v ss2 200 - 530 +934.6 v ss2 201 - 450 +934.6 v ss2 202 - 370 +934.6 v ss2 203 - 290 +934.6 v ss2 204 - 210 +934.6 v ss2 205 - 130 +934.6 v ss2 206 - 50 +934.6 v ss2 207 +30 +934.6 v ss2 208 +110 +934.6 v ss2 209 +190 +934.6 v ss2 210 +270 +934.6 v ss2 211 +350 +934.6 v ss2 212 +430 +934.6 v ss2 213 +510 +934.6 v ss1 214 +670 +934.6 v ss1 215 +750 +934.6 v ss1 216 +830 +934.6 v ss1 217 +910 +934.6 test1 218 +1150 +934.6 test5 219 +1630 +934.6 test4 220 +2030 +934.6 v ss1 221 +2110 +934.6 v ss1 222 +2190 +934.6 test3 223 +2270 +934.6 v lcdin 224 +2510 +934.6 v lcdin 225 +2590 +934.6 v lcdin 226 +2670 +934.6 v lcdin 227 +2750 +934.6 v lcdin 228 +2830 +934.6 v lcdin 229 +2910 +934.6 v lcdout 230 +3070 +934.6 v lcdout 231 +3150 +934.6 symbol pad coordinates xy
2004 feb 23 34 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 v lcdout 232 +3230 +934.6 v lcdout 233 +3310 +934.6 v lcdout 234 +3390 +934.6 v lcdout 235 +3470 +934.6 v lcdout 236 +3550 +934.6 vlcdsense 237 +3630 +934.6 alignment marks alignment mark 1 +5185 - 910.8 alignment mark 2 - 5185 - 910.8 alignment mark 3 - 4160 +909.7 alignment mark 4 +4160 +909.7 symbol pad coordinates xy
2004 feb 23 35 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 2004 feb 23 35 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mgt653 n.c. n.c. n.c. n.c. n.c. alignment mark 3 alignment mark 4 alignment mark 1 alignment mark 2 pad no.1 t3 t4 t5 t1 t2 sclk res sce d/c sdin osc v dd3 v ss1 v ss1 v ss2 v dd2 v dd1 v lcdin v lcdout v lcdsense pcf8812 x y 0, 0 row 33 row 50 col 101 col 76 col 50 col 25 col 0 . . . . . . . . . . . . row 51 row 64 . . . . . . row 32 row 19 . . . . . . row 18 row 0 . . . . . . fig.20 bonding pad locations. pcf8812u/2da/2 (1) the alignment marks are circular with a diameter of 90 m m. (2) maximum chip size: 1.92 9.84 mm. pcf8812u/2/f1 (1) the alignment marks are circular with a diameter of 100 m m. (2) maximum chip size: 2.1 10.9 mm.
2004 feb 23 36 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 17 tray information handbook, full pagewidth mgt651 d f e x y a g h 1,1 x,1 2,1 1,2 1,3 1,y x,y 2,2 3,1 c b k l m j a a section a-a fig.21 tray details. handbook, halfpage mgt652 pc8812 fig.22 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to fig.20 for the orientation and position of the type name on the die surface.
2004 feb 23 37 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 17.1 tray dimensions pcf8812u/2da/2 pcf8812/2/f1 dimension description value a pocket pitch; x direction 13.97 mm b pocket pitch; y direction 4.06 mm c pocket width; x direction 9.94 mm d pocket width; y direction 2.02 mm e tray width; x direction 50.8 mm f tray width; y direction 50.8 mm g distance from cut corner to pocket (1 and 1) centre 11.43 mm h distance from cut corner to pocket (1 and 1) centre 5.08 mm j tray thickness 3.96 mm k tray cross-section 1.78 mm l tray cross-section 2.49 mm m pocket depth 0.89 mm x no. pockets in x direction 3 y no. pockets in y direction 11 dimension description value a pocket pitch; x direction 13.77 mm b pocket pitch; y direction 4.37 mm c pocket width; x direction 11.04 mm d pocket width; y direction 2.24 mm e tray width; x direction 50.8 mm f tray width; y direction 50.8 mm g distance from cut corner to pocket (1 and 1) centre 11.68 mm h distance from cut corner to pocket (1 and 1) centre 5.74 mm j tray thickness 3.96 mm k tray cross-section 1.78 mm l tray cross-section 2.49 mm m pocket depth 0.89 mm x no. pockets in x direction 3 y no. pockets in y direction 10
2004 feb 23 38 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 18 device protection diagram handbook, full pagewidth v ss2 v ss1 v dd1 v dd3 v lcdin v lcdout v lcdsense v ss1 v dd1 t3, t2 v ss1 v ss1 v ss2 v dd2 v ss1 v ss2 mgt650 v lcdin col 0-101/ row 0-64 1 per block v ss1 v ss1 v dd1 v ss1 sdin sclk sce d/c osc res t1, t4, t5 fig.23 device protection diagram.
2004 feb 23 39 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 19 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 20 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 feb 23 40 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8812 bare die ? all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r15/02/pp 41 date of release: 2004 feb 23 document order number: 9397 750 12333

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